Conventional binary arithmetic circuits perform arithmetic operations, particularly subtraction and negation, in an indirect and inefficient manner. Subtraction has been performed by inverting a subtrahend number to form a one's complement of the subtrahend, adding the inverted subtrahend to a minuend number, and then incrementing the addition result. The incrementing of the addition result is typically accomplished by supplying a carry pulse to an adder when a subtraction is performed. A simple negation has been treated as a special subtraction problem with the minuend forced to equal zero. Thus, the same indirect steps are involved in obtaining a two's complement negation of an incoming number. Often, additional enabling combinatorial logic is required to selectively invert the subtrahend and to selectively apply the carry pulse when a subtraction or negation operation is required and to prevent inversion of the subtrahend and addition of a carry pulse when addition and other arithmetic operations are required.
In many situations, the indirect techniques for performing subtraction and negation operations are undesirable. These indirect techniques often require an undesirably large amount of circuit area or number of components for their implementation. Moreover, these indirect techniques often cause the propagation delay between the time when an incoming number is valid and the time when the subtraction or negation operation results are valid to be undesirably long.